Mitsubishi Electric L02SCPU User's Manual And Reference page 126

Melsec-l series, cpu module
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(a) When only a step number is specified
Monitor data is collected when the status immediately before execution of the specified step becomes the
specified status.
• When the operation of the specified step changes from the non-execution status to the execution status:
<>
• When the operation of the specified step changes from the execution status to the non-execution status:
<>
• Always when the operation of the specified step is being executed only: <ON>
• Always when the operation of the specified step is not being executed only: <OFF>
• Always regardless of the status of the operation of the specified step: <Always>
● If a step between the AND/OR blocks is specified as a monitor condition, monitor data is collected when the status
immediately before execution of the specified step becomes the specified status by the LD instruction in the block. The
monitoring timing depends on the ladder of the specified step. The following shows examples of monitoring when the
step 2 is on (Step No. [2] = <ON>).
When the step 2 is connected by the AND
instruction
When the step 2 is connected in the middle of the
AND/OR block
When the start of a ladder block other than the
step 0 is specified for the step number as a
detailed condition
● When "0" is specified as the step No., set the condition to "Always".
124
Condition
When both X0 and X1 are on, the monitor execution condition is
established.
Ladder mode
X0
X1
X2
0
When X1 is on, the execution condition is established. (The on/off status
of X0 does not affect the establishment of the monitor execution
condition.)
Ladder mode
X0
X1
X2
0
X3
Monitor data is collected when the execution status of the instruction
immediately before execution becomes the specified status. If (Step No.
[2] = <ON>) is specified in the following ladder, monitor data is collected
when OUT Y10 turns on.
Ladder mode
X0
0
X1
2
Description
List mode
Step 2
0
LD
1
AND X1
Y20
2
AND X2
3
OUT Y20
List mode
0
LD
Step 2
1
LD
2
AND X2
Y20
3
OR
4
ANB
5
OUT Y20
List mode
0
LD
Y10
1
OUT Y10
2
LD
Y11
3
OUT Y11
XO
XO
X1
X3
XO
X1

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