Appendix-4 Memory Map - Fuji Electric micrex-sx SPH User Manual

Micrex-sx series pulse train positioning control combined module
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2) Memory map of NP1F-MP2
Address No.
14
15
0
Ch1 Bit data signal
+1
Ch1 Bit data signal
+2
Ch1 Current value data 1
+3
Ch1 Current value data 2
+4
Current command value read
+5
Current command value read
+6
Ch2 Bit data signal
+7
Ch2 Bit data signal
+8
Ch2 Current value data 1
+9
Ch2 Current value data 2
+10
Current command value read
+11
Current command value read
+12
External pulse input counter P
+13
Module detection time P
+14
Ch1 Bit command signal
+15
Ch1 Bit command signal
+16
Ch1 Set value
+17
Ch1 Set value
+18
Ch2 Bit command signal
+19
Ch2 Bit command signal
+20
Ch2 Set value
+21
Ch2 Set value
The I/O area of NP1F-MP2 occupies 22 words.
13
12
11
10
9
lower word
PC < = = MP2
upper word
PC < = = MP2
lower word
PC < = = MP2
upper word
PC < = = MP2
lower word
PC < = = MP2
upper word
PC < = = MP2
lower word
PC < = = MP2
upper word
PC < = = MP2
PC < = = MP2
lower word
PC = = > MP2
upper word
PC = = > MP2
lower word
PC = = > MP2
upper word
PC = = > MP2
lower word
PC = = > MP2
upper word
PC = = > MP2
lower word
PC = = > MP2
upper word
PC = = > MP2
App.-11

Appendix-4 Memory Map

8
7
6
5
4
lower word
PC < = = MP2
upper word
PC < = = MP2
lower word
PC < = = MP2
upper word
PC < = = MP2
PC < = = MP2
3
2
1
0
Remarks
MP2
Read area
MP2
Write area
PC
PC

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