Section 5 Memory Map - Fuji Electric micrex-sx SPH User Manual

Section 5 Memory Map

5-1 NP1F-MP1/NP1F-MP2 Memory Map (Internal Memory List) .................................... 5-1
5-2 NP1F-MP1 I/O Area ..................................................................................................... 5-2
5-2-1 NP1F-MP1 (read area: address No. 0 to No. 9) .................................................................... 5-3
(1) Bit data signal (status signal, address No. "0," lower word) ..................................................................... 5-3
(2) Bit data signal (Status signal, address No. 1, upper word) ................................................................... 5-12
(3) Current value read (Address No. 2: lower word; address No. 3: upper word) ........................................ 5-16
(4) Current command value read (Address No. 4: lower word; address No. 5: upper word) ....................... 5-16
(5) External pulse input counter (Address No. 8) ....................................................................................... 5-16
(6) Module detection time (Address No. 9) ................................................................................................. 5-17
(7) Current external pulse data (Address No. 6: lower word; address No. 7: upper word) .......................... 5-17
5-2-2 NP1F-MP1 (Write area: address Nos. 10 to 13) ................................................................. 5-18
(1) Bit command signal (write signal, address No. 10, lower word) ............................................................ 5-18
(2) Bit command signal (Write signal, address No. 11, upper word) .......................................................... 5-30
(3) Set value area (Write signal, address Nos. 12 and 13) ......................................................................... 5-34
5-3 I/O Area of NP1F-MP2 ............................................................................................... 5-35
5-3-1 NP1F-MP2 (Read area: address No. 0 to No. 13) ............................................................... 5-36
(1) Ch1 bit data signal (Status signal, address No. 0, lower word) ............................................................. 5-36
(2) Ch1 bit data signal (Status signal, address No. 1, upper word) ............................................................ 5-46
(3) Ch1 current value read (Address No. 2: lower word; address No. 3: upper word) ................................. 5-50
(4) Current command value read (Address No. 4: lower word; address No. 5: upper word) ....................... 5-50
(5) Ch2 bit data signal (Status signal, address No. 6, lower word) ............................................................. 5-51
(6) Ch2 bit data signal (status signal, address No. 7, upper word) ............................................................. 5-61
(7) Current value read (Address No. 8: lower word; address No. 9: upper word) ........................................ 5-65
(8) Current command value read (Address No. 10: lower word; address No. 11: upper word) ................... 5-65
(9) External pulse input counter (Address No. 12) ..................................................................................... 5-65
(10) Module detection time (Address No. 13) ............................................................................................. 5-66
5-3-2 NP1F-MP2 (Write area: address Nos. 14 to 21) ................................................................. 5-67
(1) Ch1 bit command signal (Write area, address No. 14, lower word) ...................................................... 5-67
(2) Ch1 bit command signal (Write signal, address No. 15, upper word) ................................................... 5-79
(3) Ch1 set value area (Write signal, address Nos. 16 and 17) .................................................................. 5-82
(4) Ch2 bit command signal (write signal, address No. 18, lower word) ..................................................... 5-83
(5) Ch2 bit command signal (Write signal, address No. 19, upper word) ................................................... 5-95
(6) Set value area (Write signal, address Nos. 20 and 21) ......................................................................... 5-98
5-4 Setting Method and Effective Bits of Individual Register ..................................... 5-99
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