Np1F-Mp1/Np1F-Mp2 Memory Map (Internal Memory List) - Fuji Electric micrex-sx SPH User Manual

Micrex-sx series pulse train positioning control combined module
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The memory map for the NP1F-MP1/NP1F-MP2 is shown below.
Data is passed from the CPU via an SX bus and I/O area (I/Q area).
[CPU program]
SX bus
I/O area
(occupies 22/14 words)
5-1 NP1F-MP1/NP1F-MP2 Memory Map
N
P
1
A
d
d
0
1
Write
2
3
Read
4
5
6
7
8
:
:
:
3
1
Section 5 Memory Map
(Internal Memory List)
- F
M
P
1
N /
P
1
- F
M
P
2
m
e
m
o
y r
e r
s
s
N
. o
N
a
m
e
T
a
g r
e
f t
e r
q
u
e
n
B
a
s
e
f
e r
q
u
e
n
y c
C
r u
e r
n
f t
e r
q
u
e
C
o
m
m
a
n
d
p
u
s l
D
e
c
l e
r e
t a
o i
n
p
A
c c
l e
r e
t a
o i
n
d /
e
A
c c
l e
r e
t a
o i
n
d /
e
S
p
e
e
d
m
u
t l
p i
c i l
C
o
m
m
a
n
d
p
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s l
:
:
:
R
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v r
e
d
5-1
m
a
p
(
n I
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) y
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i o
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t s i
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1
c
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t a
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2
t a
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c
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