Data Direction Register (Ddr); Pin Functions - Hitachi H8/3152 Hardware Manual

9.2.2

Data Direction Register (DDR)

Bit:
Initial value:
Read/Write:
The data direction register specifies the direction (input or output) of the I/O ports.
Bit 7—Data Direction Register Bit 7 (DDR7): Specifies the direction of the I/O-1 signal: 1
selects output; 0 selects input.
This bit can be written but not read. If read, it always returns the value 1, regardless of its true
value.
A reset clears this bit to 0, making I/O-1 an input port.
Bit 6—Data Direction Register Bit 6 (DDR6): Specifies the direction of the I/O-2 signal: 1
selects output; 0 selects input.
This bit can be written but not read. If read, it always returns the value 1, regardless of its true
value.
A reset clears this bit to 0, making I/O-2 an input port.
Bits 5 to 0—Reserved: Always read as 1 and cannot be written to.
Although not used at present, reserved bits may be used in the future. When writing to DDR, write
0 to these bits.
The DR and DDR contents are retained in sleep mode as long as the necessary voltage is supplied,
but the I/O ports are placed in the output-disabled state, with input pull-up MOS connected,
regardless of the value in the I/O port direction register (DDR).
Note: The DDR7 and DDR6 bits are always read as 1. Therefore, when writing to these bits, use
the MOV instruction instead of the bit manipulation instruction such as BSET or BCLR.
9.3

Pin Functions

The I/O-1/IRQ and I/O-2/IRQ pins function as external interrupt input pins in sleep mode. The
same exception handling vector is assigned to both pins.
Table 9.2 shows the I/O-1/IRQ and I/O-2/IRQ pin states in each operating mode.
100
7 6
DDR7 DDR6
0 0
W W
5 4 3
— — —
— — —
— — —
2 1 0
— — —
— — —
— — —