Addressing Modes - Hitachi H8/3152 Hardware Manual

2.4

Addressing Modes

2.4.1 Addressing Modes
The H8/300 CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a
subset of these addressing modes.
Table 2.1 Addressing Modes
No. Addressing Mode
(1) Register direct
(2) Register indirect
(3) Register indirect with displacement
(4) Register indirect with post-increment
Register indirect with pre-decrement
(5) Absolute address
(6) Immediate
(7) Program-counter relative
(8) Memory indirect
(1) Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general
register containing the operand.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
(2) Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general
register containing the address of the operand.
(3) Register Indirect with Displacement—@(d:16, Rn): The instruction has a second word
(bytes 3 and 4) containing a displacement which is added to the contents of the specified general
register to obtain the operand address.
This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address
must be even.
Symbol
Rn
@Rn
@(d:16, Rn)
@Rn+
@–Rn
@aa:8 or @aa:16
#xx:8 or #xx:16
@(d:8, PC)
@@aa:8
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