Register Configuration; Register Descriptions; Data Register (Dr) - Hitachi H8/3152 Hardware Manual

9.1.2

Register Configuration

Table 9.1 lists the I/O port registers.
Table 9.1 I/O Port Registers
Name
Data register
Data direction register
9.2

Register Descriptions

9.2.1

Data Register (DR)

Bit:
Initial value:
Read/Write:
The data register latches the output data.
Bit 7—Data Register Bit 7 (DR7): Latches I/O port output data. When DDR7 = 1 (selecting
output), the value of the DR7 bit is output on the I/O-1 pin.
When DR is read, if DDR7 = 0 (input), the logic level of the I/O-1 signal is read directly. If DDR7
= 1 (output), the value in the DR7 latch is read.
The value of DR7 after a reset is undetermined.
Bit 6—Data Register Bit 6 (DR6): Latches I/O port output data. When DDR6 = 1 (selecting
output), the value of the DR6 bit is output on the I/O-2 pin.
When DR is read, if DDR6 = 0 (input), the logic level of the I/O-2 signal is read directly. If DDR6
= 1 (output), the value in the DR6 latch is read.
The value of DR6 after a reset is undetermined.
Bits 5 to 0—Reserved: Always read as undetermined and cannot be written to.
Although not used at present, reserved bits may be used in the future. When writing to DR, write 0
to these bits.
Abbr.
DR
DDR
7 6
DR7 DR6
— —
R/W R/W
R/W
R/W
W
5 4 3
— — —
— — —
— — —
Address
H'FFFE
H'FFFF
2 1 0
— — —
— — —
— — —
99