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Table 2.2
Effective Address Calculation
Addressing Mode,
No.
Instruction Format
Register direct Rn
1
15
8
op
2
Register indirect
15
op
3
Register indirect
with displacement
@(d:16, Rn)
15
op
disp
Register indirect
4
with post-increment
@Rn+
15
op
Register indirect
with pre-decrement
@–Rn
15
op
20
Effective Address
Calculation
7
4
3
0
regm
regn
15
7
6
4
3
0
reg
15
7
6
4
3
0
reg
15
7
6
4
3
0
reg
15
7
6
4
3
0
reg
* 1 for a byte operand,
2 for a word operand
16-bit register contents
16-bit register contents
16-bit register contents
16-bit register contents
1 or 2*
16-bit register contents
1 or 2*
Effective Address
3
0
regm
Operands are contained
in registers m and n
0
15
0
15
0
15
0
15
3
0
regn
0
0
0
0
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