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5.1
Overview
Specify whether to operate or stop the WDT for each ROM code. When stopped, the WDT does
not issue interrupts.
The H8/3150 series has a single-channel watchdog timer (WDT) for monitoring system
operations; that is, monitoring whether the application program is properly executed and whether
the EEPROM is correctly written to.
The WDT issues a UDF interrupt at a required interval. The UDF interrupt routine can monitor the
PC in the stack area to check whether the application program was executed in the defined area.
The WDT also issues an EWE interrupt before an EEPMOV instruction is executed. The EWE
interrupt routine can monitor the instructions in the area pointed to by the PC that is saved in the
stack area, to check whether an EEPMOV instruction will be executed in the correct procedure
and with the correct data. UDF and EWE interrupts are not masked by the I bit setting in the CCR.
Setting the halt flag after the above checking is completed stops all the on-chip functions. To exit
from this state and enter the reset state, input a low-level signal to the RES pin.
5.1.1
Features
• Reloads the counter value when the write instruction at the defined area is executed.
• Issues a UDF interrupt at a required interval.
• Issues an EWE interrupt before an EEPMOV instruction is executed.
• Stops the on-chip functions (enters reset state) when the halt flag is set.
• One of four counter clock sources can be selected.
Note: When the WDT stops, do not access WDT control registers.
Section 5 Watchdog Timer (WDT)
57
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