Hitachi H8/3152 Hardware Manual page 131

TCSR Timer Control/Status Register
Bit 7
UDF
0
Initial value
R/W
Read/Write
Underflow Flag
[Clearing condition]
0
When RTE instruction is executed while UDF = 1
1 [Setting conditon]
When TCNT underflow occurs (H'00 → H'FF)
Note: Only 1 can be written to bit 6 to set the flag.
TCNT Timer Counter
Bit 7
Initial value 1
Read/Write R/W
132
6 5
EWE —
0
1
R/(W)* R
ECR Write Enable
0 [Clearing condition]
When EEPMOV instruction execution ends
[Setting conditon]
1
When 1 is written to this bit while it is 0
6 5
1 1
R/W R/W
Timer count
4 3
HLT —
0 1
R/W R
Halt Flag
0 Normal operation
1 On-chip functions stop
4 3
1 1
R/W R/W R/W
WDT
2 1
— CS1 CS0
1 0
R/W
R R/W
Clock Select 1 and 0
0 0 CLK/32
1 CLK/64
1 0 CLK/128
1 CLK/256
WDT
2 1
1 1
R/W R/W
0
0
0
1