Timer Counter Write Address (Tcwa) - Hitachi H8/3152 Hardware Manual

Bit 5—Reserved: Always read as 1 and cannot be written to. Although not used at present, the
reserved bit may be used in the future. When writing to TCSR, write 0 into bit 5.
Bit 4—Halt Flag (HLT): Controls operation of all the on-chip functions. When the HLT bit is
set to 1, all the on-chip functions stop. The HLT bit is set to 1 when a TCNT underflow occurs
while UDF = 1, or 1 is written to the EWE bit while UDF = 1, or 1 is written to the EWE bit while
EWE = 1.
Bit 4: HLT Description
0 Normal operation
1 All the on-chip functions stop operating. Operation returns from halt state when
a low-level signal is input to the RES pin.
Bits 3 and 2—Reserved: Always read as 1 and cannot be written to. Although not used at
present, the reserved bits may be used in the future. When writing to TCSR, write 0 into bits 3 and
2.
Bits 1 and 0—Clock Select 1 and 0 (CS1 and CS0): Select one from four clock sources
obtained by dividing the CLK pin input, as the input to TCNT.
Bit 1: CS1 Bit 0: CS0
0 0
1
1 0
1
5.2.3

Timer Counter Write Address (TCWA)

TCWA has four address bits and one control bit, which are readable and writable. Bits 3 to 1
cannot be written to.
TCWA is initialized to H'FF at reset, but not reset in sleep mode. TCWA can be written to only
once when 0 is written to the WAD bit at the same time, and before TCSR is written to. Once
written to, TCWA cannot be written to again until the chip is reset by a low-level input to the RES
pin.
Bit:
Initial value:
Read/Write:
Description
CLK/32
CLK/64
CLK/128
CLK/256
7 6
IA15 IA14 IA13
1 1
R/W R/W R/W
5 4 3
IA12 —
1 1 1
R/W R
(Initial value)
(Initial value)
2 1 0
— — WAD
1 1 1
R R R/W
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