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Condition registers
As
Figure 11-4
shows, some register sets have a condition register. A condition register is a
real-time, read-only register that constantly updates to reflect the present operating conditions
of the instrument. For example, while a measurement is being performed, bit B4 (Meas) of the
Operation Condition Register is set. When the measurement is completed, bit B4 clears.
Use the :CONDition? query commands in the STATus Subsystem to read the condition
registers. See
Section 14
for more information.
Event registers
As
Figure 11-4
shows, each status register set has an event register. An event register is a
latched, read-only register whose bits are set by the corresponding condition register. Once a bit
in an event register is set, it remains set (latched) until the register is cleared by a specific clearing
operation. The bits of an event register are logically ANDed with the bits of the corresponding
enable register and applied to an OR gate. The output of the OR gate is applied to the Status Byte
Register.
Use the *ESR? Common Command to read the Standard Event Register. All other event
registers are read using the EVENt? query commands in the STATus Subsystem. See
for more information.
An event register is cleared when it is read. The following operations clear all event registers:
•
Cycling power
•
Sending *CLS
Enable registers
As
Figure 11-4
shows, each status register set has an enable register. An enable register is
programmed by you and serves as a mask for the corresponding event register. An event bit is
masked when the corresponding bit in the enable register is cleared (0). When masked, a set bit
in an event register cannot set a bit in the Status Byte Register (1 AND 0 = 0).
To use the Status Byte Register to detect events (i.e., serial poll), you must unmask the events
by setting (1) the appropriate bits of the enable registers.
To program and query the Standard Event Status Register, use the *ESE and *ESE? Common
Commands respectively. All other enable registers are programmed and queried using the
:ENABle and :ENABle? commands in the STATus Subsystem. See
information.
An enable register is not cleared when it is read. The following operations affect the enable
registers:
•
Cycling power — Clears all enable registers
•
:STATus:PRESet clears the following enable registers:
•
Operation Event Enable Register
•
Questionable Event Enable Register
•
Measurement Event Enable Register
•
*ESE 0 — Clears the Standard Event Status Enable Register
Remote Operation
11-15
Section 14
Section 14
for more
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