GE MiCOM P40 Agile Technical Manual page 22

Table of Figures
Figure 39: Modification of current pickup level for voltage restrained overcurrent protection
Figure 40: Voltage dependant overcurrent logic (Phase A to phase B)
Figure 41: Selecting the current threshold setting
Figure 42: Cold Load Pickup logic
Figure 43: Selective Logic
Figure 44: Selecting the timer settings
Figure 45: Negative Sequence Overcurrent logic - non-directional operation
Figure 46: Composite Earth Fault Start Logic
Figure 47: Negative Sequence Overcurrent logic - directional operation
Figure 48: Non-directional EF logic (single stage)
Figure 49: IDG Characteristic
Figure 50: Directional EF logic with neutral voltage polarization (single stage)
Figure 51: Directional Earth Fault logic with negative sequence polarisation (single stage)
Figure 52: Current level (amps) at which transient faults are self-extinguishing
Figure 53: Earth fault in Petersen Coil earthed system
Figure 54: Distribution of currents during a Phase C fault
Figure 55: Phasors for a phase C earth fault in a Petersen Coil earthed system
Figure 56: Zero sequence network showing residual currents
Figure 57: Phase C earth fault in Petersen Coil earthed system: practical case with resistance
present
Figure 58: Non-directional SEF logic
Figure 59: SEF Any Start Logic
Figure 60: EPATR B characteristic shown for TMS = 1.0
Figure 61: Types of directional control
Figure 62: Resistive components of spill current
Figure 63: Operating characteristic for Icos
Figure 64: Directional SEF with VN polarisation (single stage)
Figure 65: Current distribution in an insulated system with C phase fault
Figure 66: Phasor diagrams for insulated system with C phase fault
Figure 67: Positioning of core balance current transformers
Figure 68: Thermal overload protection logic diagram
Figure 69: Spreadsheet calculation for dual time constant thermal characteristic
Figure 70: Dual time constant thermal characteristic
Figure 71: Broken conductor logic
Figure 72: Blocked Overcurrent logic
Figure 73: Blocked Earth Fault logic
Figure 74: Simple busbar blocking scheme
Figure 75: Simple busbar blocking scheme characteristics
Figure 76: 2nd Harmonic Blocking Logic (POC Input)
Figure 77: 2nd Harmonic Blocking Logic (SEF Input)
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