Chapter 13 - Autoreclose
7.2.3
BLOCKING SIGNAL LOGIC
CB Fail Alarm
Block AR
Relay 3 Output
IREF> Trip
I2>1 Trip
Broken Line Trip
Thermal Trip
V<1 Trip
V<2 Trip
V>1 Trip
1
V>2 Trip
VN>1 Trip
VN>2 Trip
Trip V2>2
Stg1 f+t Trp
Stg1 f+Df/Dt Trp
Stg1 df/dt +t Trp
Stg1 f+df /dt Trp
V00515
Figure 149: Blocking signal logic
7.2.4
SHOTS EXCEEDED LOGIC
Main Protection Start
SC Count >= Main Shots
SEF Protection Start
SC Count >= SEF Shots
V00504
Figure 150: Shots Exceeded logic
292
I>3 Trip
&
I>3 AR
Block AR
I>4 Trip
&
I>4 AR
Block AR
I>6 Trip
&
I>6 AR
Block AR
IN1>3 Trip
&
IN1>3 AR
Block AR
IN1>4 Trip
&
1
IN1>4 AR
Block AR
IN2>3 Trip
IN2>3 AR
&
Block AR
IN2>4 Trip
&
IN2>4 AR
Block AR
ISEF>3 Trip
&
ISEF>3 AR
Block AR
ISEF>4 Trip
&
ISEF>4 AR
Block AR
S
&
Q
R
&
S
Q
R
&
1
Note: This diagram does not show all stages . Other stages follow similar
principles.
P14x
Block autoreclose
Main High Shots
SEF High Shots
P14xEd1-TM-EN-1