Nrst And Npor Pin Characteristics; Table 47. Nrst Pin Characteristics; Figure 22. Recommended Nrst Pin Protection - STMicroelectronics STM32F038C6 Manual

Electrical characteristics
6.3.14

NRST and NPOR pin characteristics

NRST pin characteristics
The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor, R
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 18: General operating
Symbol Parameter
V NRST input low level voltage
IL(NRST)
V NRST input high level voltage
IH(NRST)
NRST Schmitt trigger voltage
V
hys(NRST)
hysteresis
Weak pull-up equivalent
R
(2)
PU
resistor
V NRST input filtered pulse
F(NRST)
V NRST input not filtered pulse
NF(NRST)
1. Data based on design simulation only. Not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
1. The external capacitor protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
Table 47: NRST pin
NPOR pin characteristics
The NPOR pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor to the V
Unless otherwise specified, the parameters given in
performed under ambient temperature and supply voltage conditions summarized in
Table 18: General operating
68/102
.
PU
conditions.

Table 47. NRST pin characteristics

Conditions
-
-
-
V
=
IN
-
-

Figure 22. Recommended NRST pin protection

characteristics. Otherwise the reset will not be taken into account by the device.
, R .
DDA PU
conditions.
DocID026079 Rev 3
Min
-
0.445 V +0.398
DD
-
V 25
SS
-
(1)
700
Table 48
STM32F038x6
Typ Max
- 0.3 V +0.07
DD
(1)
- -
200 -
40 55
(1)
- 100
- -
max level specified in
IL(NRST)
below are derived from tests
Unit
(1)
V
mV
kΩ
ns
ns