Figure 23. I 2 S Slave Timing Diagram (Philips Protocol); Figure 24. I 2 S Master Timing Diagram (Philips Protocol) - STMicroelectronics STM32L162RC Manual

Electrical characteristics
ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of
(I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition.
1. Measurement points are done at CMOS levels: 0.3 × V
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
1. Guaranteed by characterization results.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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2
Figure 23. I S slave timing diagram (Philips protocol)
2
Figure 24. I S master timing diagram (Philips protocol)
DocID022881 Rev 10
STM32L162VC, STM32L162RC
and 0.7 × V .
DD DD
(1)
(1)