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STM32L162VC, STM32L162RC
Peripheral
APB2
AHB
All enabled
I
DD (RTC)
I
DD (LCD)
I
DD (ADC)
I
DD (DAC)
I
DD (COMP1)
I
DD (COMP2)
I
DD (PVD / BOR)
I
DD (IWDG)
1. Data based on differential I
enabled, in the following conditions: f
(range 3), f
each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling.
Table 25. Peripheral current consumption
Range 1,
V
VOS[1:0] =
SYSCFG &
RI
TIM9
TIM10
TIM11
(2)
ADC
SPI1
USART1
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOH
CRC
AES
FLASH
DMA1
DMA2
(4)
(5)
Slow mode
Fast mode
(6)
measurement between all peripherals OFF an one peripheral with clock
DD
= 64kHz (Low-power run/sleep), f
HCLK
DocID022881 Rev 10
Typical consumption, V
Range 2,
=
V
=
CORE
CORE
1.8 V
1.5 V
VOS[1:0] =
01
10
2.6
2.0
7.9
6.4
5.9
4.7
5.9
4.6
10.5
8.3
4.3
3.4
8.8
7.1
4.3
3.3
4.3
3.5
4.0
3.2
4.1
3.3
4.2
3.4
3.7
3.0
0.8
0.6
5
4
11.1
9.4
15.6
12.7
16.3
13.4
192
158
0.4
3.1
1450
340
0.16
2.6
0.25
= 32 MHz (range 1), f
HCLK
= f
APB1
HCLK
(1)
(continued)
= 3.0 V, T
= 25 °C
DD
A
Range 3,
V
=
Low-power
CORE
1.2 V
sleep and
VOS[1:0] =
run
11
1.6
2.0
5.0
6.4
3.8
4.7
3.7
4.6
6.6
8.3
2.8
3.4
5.6
7.1
2.6
3.3
2.8
3.5
2.5
3.2
2.5
3.3
2.7
3.4
2.3
3.0
0.5
0.6
3
4
(3)
8
-
10
12.7
10.5
13.4
123
148.6
2
5
= 16 MHz (range 2), f
HCLK
, f
= f
, default prescaler value for
APB2
HCLK
Unit
µA/MHz
(f
)
HCLK
µA
= 4 MHz
HCLK
65/123
104
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