Figure 2. Clock Tree - STMicroelectronics STM32L151CB Manual

STM32L151xx, STM32L152xx
●
Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI and a software
interrupt is generated if enabled.
● Clock-out capability (MCO: microcontroller clock output): it outputs one of the
internal clocks for external use by the application.
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 32 MHz. See
Figure 2.
2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either
24 MHz or 32 MHz.
Figure 2
Clock tree
Doc ID 17659 Rev 6
for details on the clock tree.
Functional overview
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