Reset And Supply Management; Power Supply Schemes; Power Supply Supervisor; Voltage Regulator - STMicroelectronics STM32L151CB Manual

STM32L151xx, STM32L152xx
3.3

Reset and supply management

3.3.1

Power supply schemes

●
V
DD
Provided externally through V
●
V
SSA
and PLL (minimum voltage to be applied to V
V
DDA
3.3.2

Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
For devices operating between 1.8 and 3.6 V, the BOR is always active at power-on and
ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached, the
option byte loading process starts, either to confirm or modify default thresholds, or to
disable BOR permanently (in which case, the V
BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the
power consumption in Stop mode, it is possible to automatically switch off the internal
reference voltage (V
below a specified threshold, V
circuit.
Note: For devices operating between 1.65 V and 3.6 V, the BOR is permanently disabled.
Consequently, the start-up time at power-on can be decreased down to 1ms typically.
The device features an embedded programmable voltage detector (PVD) that monitors the
V /V
DD DDA
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when V
V /V
DD DDA
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
3.3.3

Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.
●
MR is used in Run mode (nominal regulation)
●
LPR is used in the Low-power run, Low-power sleep and Stop modes
●
Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost are lost except for the standby circuitry (wakeup logic,
IWDG, RTC, LSI, LSE crystal 32K osc, RCC_CSR).
= 1.65 to 3.6 V: external power supply for I/Os and the internal regulator.
, V = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
DDA
and V must be connected to V
SSA
) in Stop mode. The device remains in reset mode when V
REFINT
POR/PDR
power supply and compares it to the V
is higher than the V
PVD
Doc ID 17659 Rev 6
pins.
DD
is 1.8 V when the ADC is used).
DDA
and V
DD SS
min value at power down is 1.65 V). Five
DD
or V , without the need for any external reset
BOR
threshold. This PVD offers 7 different
PVD
/V drops below the V
DD DDA
threshold. The interrupt service routine can then generate
Functional overview
, respectively.
threshold and/or when
PVD
is
DD
15/109