Table 45. Spi Characteristics - STMicroelectronics STM32L151CB Manual

Electrical characteristics
SPI characteristics
Unless otherwise specified, the parameters given in the following table are derived from
tests performed under ambient temperature, f
conditions summarized in
Refer to
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 45.
Symbol
f
SCK
1/t
c(SCK)
t
r(SCK)
t
f(SCK)
DuCy(SCK)
t
su(NSS)
t
h(NSS)
t
w(SCKH)
t
w(SCKL)
t
su(MI)
t
su(SI)
t
h(MI)
t
h(SI)
(3)
t
a(SO)
t
dis(SO)
(2)
t
v(SO)
(2)
t
v(MO)
(2)
t
h(SO)
(2)
t
h(MO)
1. Remapped SPI1 characteristics to be determined.
2. Based on characterization, not tested in production.
3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the
data.
4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the
data in Hi-Z.
80/109
Table
Section 6.3.11: I/O current injection characteristics
SPI characteristics
Parameter
SPI clock frequency
SPI clock rise and fall
time
SPI slave input clock duty
cycle
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
(4)
Data output disable time
Data output valid time
Data output valid time
Data output hold time
frequency and V
PCLKx
9.
(1)
Conditions
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Slave mode
Slave mode
Master mode, f
presc = 4
Master mode
Slave mode
Master mode
Slave mode
Slave mode, f
PCLK
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
Doc ID 17659 Rev 6
STM32L151xx, STM32L152xx
supply voltage
DD
for more details on the
Min
30
4t
PCLK
2t
PCLK
= 16 MHz,
PCLK
TBD
5
5
5
4
= 20 MHz 0
TBD
TBD
TBD
(2)
Max Unit
16
MHz
16
TBD ns
70 %
TBD
ns
3t
PCLK
TBD
TBD
TBD