Xilinx Vivado MIPI CSI-2 Manuals

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Xilinx Vivado MIPI CSI-2 Product Manual

Xilinx Vivado MIPI CSI-2 Product Manual (91 pages)

Receiver Subsystem v4.0

Brand: Xilinx | Category: Receiver | Size: 4 MB

Table of Contents

Table of Contents
2
Features
4
IP Facts
4
- Overview
  5
- Mipi D-Phy
  6
- RX Controller
  6
- Sub-Core Details
  6
Chapter 1: Overview

6
- ECC/CRC Forwarding
  8
- VCX Support
  8
- AXI Crossbar
  9
- Video Format Bridge
  9
- Pixel Packing for Multiple Data Types
  10
- Pixel Packing for Embedded Non-Image Data Types
  11
- Pixel Packing When Video Format Bridge Is Not Present
  11
- Applications
  12
  - Axi IIC
    12
  - License Checkers
    13
  - License Type
    13
- Licensing and Ordering
  13
- Unsupported Features
  13
Chapter 2: Product Specification

14
- Standards
  14
- Performance
  14
- Port Descriptions
  17
- Resource Utilization
  17
- Register Space
  21
  - RX Controller Core Registers
    21
  - Core Configuration Register
    24
  - Protocol Configuration Register
    25
  - Core Status Register
    25
  - Global Interrupt Enable Register
    26
  - Interrupt Status Register
    26
  - Incorrect Lane Configuration
    28
  - Stream Line Buffer Full
    28
  - Control Error/Escape Entry Error/Escape Ultra Low Power Mode/Stopstate
    29
  - Sot Error
    29
  - Sot Sync Error
    29
  - ECC 2-Bit Error/1-Bit Error
    29
  - VC Mapping
    30
  - Unsupported Data Type
    30
  - Frame Synchronization Error
    30
  - Frame Level Error
    30
  - Interrupt Enable Register
    31
  - Generic Short Packet Register
    32
  - VCX Frame Error Register
    32
  - Clock Lane Information Register
    34
  - Lane N Information Registers
    34
  - Image Information 1 Registers (VC0 to VC15)
    35
  - Image Information 2 Registers (VC0 to VC15)
    35
  - AXI IIC Registers
    35
  - MIPI D-PHY Registers
    36
- Shared Logic
  37
Chapter 3: Designing with the Subsystem

37
- General Design Guidelines
  37
  - Shared Logic in the Subsystem
    39
  - Shared Logic Outside Subsystem
    39
- I/O Planning
  42
- Clocking
  44
  - Subsystem Clocks
    44
  - Clocking Structure
    45
- Resets
  47
- Protocol Description
  48
- Customizing and Generating the Subsystem
  51
Chapter 4: Design Flow Steps

51
- Board Tab
  52
- Configuration Tab
  53
- Shared Logic Tab
  55
- Pin Assignment Tab
  57
- User Parameters
  59
- Clock Management
  60
- Constraining the Subsystem
  60
- Simulation
  62
- Synthesis and Implementation
  62
Chapter 5: Application Example Design

63
- Application Example Design Overview
  63
- Setup Details
  65
  - Hardware Setup
    65
  - Running the Design on the Hardware
    69
- Implementing the Example Design
  70
- Known Issues
  77
- Hardware Validation
  78
Appendix A: Verification, Compliance, and Interoperability

78
Appendix B: Debugging

81
- Finding Help on Xilinx.com
  81
- Debug Tools
  82
- Hardware Debug
  83
- Interface Debug
  84
  - AXI4-Stream Interfaces
    85
  - Sideband Information on AXI4-Stream Interfaces
    85
Appendix C: Additional Resources and Legal Notices

87
- Xilinx Resources
  87
- Documentation Navigator and Design Hubs
  87
- References
  88
- Revision History
  89
- Please Read: Important Legal Notices
  90

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