Xilinx Spartan-3 User Manual page 25

VGA Signal Timing
Generally, a counter clocked by the pixel clock controls the horizontal timing. Decoded
counter values generate the HS signal. This counter tracks the current pixel display
location on a given row.
A separate counter tracks the vertical timing. The vertical-sync counter increments with
each HS pulse and decoded values generate the VS signal. This counter tracks the current
display row. These two continuously running counters form the address into a video
display buffer. For example, the on-board fast SRAM is an ideal display buffer.
No time relationship is specified between the onset of the HS pulse and the onset of the VS
pulse. Consequently the counters can be arranged to easily form video RAM addresses, or
to minimize decoding logic for sync pulse generation.
Spartan-3 Starter Kit Board User Guide
UG130 (v1.1) May 13, 2005
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