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R
The A1 expansion connector shares connections with the 256Kx16 SRAM devices,
specifically the SRAM address lines, the OE# and WE# control signals, and the eight least-
significant data lines to SRAM IC10 only. Similarly, the JTAG chain is available on pins 36
through 40. Pin 20 is the FPGA DOUT/BUSY configuration signal and toggles during the
FPGA configuration process.
A2 Connector Pinout
The A2 expansion connector is located along the top edge of the board, on the right, as
indicated by
FPGA connections are specified in parentheses.
Most of the A2 expansion connector pins connect only with the FPGA and are not shared.
Pin 35 connects to the auxiliary clock socket, if an oscillator is installed in the socket. Pins
36 through 40 include the signals required to configure the FPGA in Master or Slave Serial
mode.
Table 13-3: Pinout for A2 Expansion Connector
Schematic Name
GND
V
(+3.3V)
CCO
PA-IO2
PA-IO4
PA-IO6
PA-IO8
PA-IO10
PA-IO12
PA-IO14
PA-IO16
PA-IO18
MA2-DB1
MA2-DB3
MA2-DB5
MA2-DB7
MA2-DSTB
MA2-WAIT
MA2-INT/GCK4
DONE
CCLK
50
in
Figure
1-2.
20
FPGA Pin
V
(all banks)
CCO
(D5)
(D6)
(E7)
(D7)
(D8)
(D10)
(B4)
(B5)
(B6)
(A7)
(A8)
(B10)
(B11)
(A12)
(A13)
(D9)
Oscillator socket
(R14)
FPGA DONE
(T15)
FPGA CCLK
Connects to (A14) via
390Ω resistor
www.xilinx.com
1-800-255-7778
Chapter 13: Expansion Connectors and Boards
Figure 13-3
provides the pinout for the A2 connector. The
Connector
FPGA Pin
1
2
3
4
(E6)
5
6
(C5)
7
8
(C6)
9
10
(C7)
11
12
(C8)
13
14
(C9)
15
16
(A3)
17
18
(A4)
19
20
(A5)
21
22
(B7)
23
24
(B8)
25
26
(A9)
27
28
(A10)
29
30
(B12)
31
32
(B13)
33
34
(B14)
(B3)
35
36
FPGA PROG_B
(N9)
37
38
FPGA INIT_B
(M11)
39
40
Spartan-3 Starter Kit Board User Guide
Schematic Name
VU (+5V)
PA-IO1
PA-IO3
PA-IO5
PA-IO7
PA-IO9
PA-IO11
PA-IO13
PA-IO15
PA-IO17
MA2-DB0
MA2-DB2
MA2-DB4
MA2-DB6
MA2-ASTB
MA2-WRITE
MA2-RESET
PROG-B
INIT
DIN
UG130 (v1.1) May 13, 2005
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