Address Bus Connections - Xilinx Spartan-3 User Manual

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The SRAM array forms either a single 256Kx32 SRAM memory or two independent
256Kx16 arrays. Both SRAM devices share common write-enable (WE#), output-enable
(OE#), and address (A[17:0]) signals. However, each device has a separate chip select
enable (CE#) control and individual byte-enable controls to select the high or low byte in
the 16-bit data word, UB and LB, respectively.
The 256Kx32 configuration is ideally suited to hold MicroBlaze instructions. However, it
alternately provides high-density data storage for a variety of applications, such as digital
signal processing (DSP), large data FIFOs, and graphics buffers.

Address Bus Connections

Both 256Kx16 SRAMs share 18-bit address control lines, as shown in
address signals also connect to the A1 Expansion Connector (see
page
Table 2-1: External SRAM Address Bus Connections to Spartan-3 FPGA
12
47).
Address Bit
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
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Chapter 2: Fast, Asynchronous SRAM
FPGA Pin A1 Expansion Connector Pin
L3
K5
K3
J3
J4
H4
H3
G5
E4
E3
F4
F3
G4
L4
M3
M4
N3
L5
Spartan-3 Starter Kit Board User Guide
Table 2-1. These
"Expansion Connectors,"
35
33
34
31
32
29
30
27
28
25
26
23
24
14
12
10
8
6
UG130 (v1.1) May 13, 2005