Xilinx Spartan-3 User Manual page 48

R
Table 13-1: Expansion Connector Features
Connector User I/O
A1 32
A2 34
B1 34
Each port offers some ability to program the FPGA on the Spartan-3 Starter Kit Board. For
example, port A1 provides additional logic to drive the FPGA and Platform Flash JTAG
chain. Similarly, ports A2 and B1 provide connections for Master or Slave Serial mode
configuration. Finally, port B1 also offers Master or Slave Parallel configuration mode.
Each 40-pin expansion header, shown in
Pin 1 on each connector is always GND. Similarly, pin 2 is always the +5V DC output from
the switching power supply. Pin 3 is always the output from the +3.3V DC regulator.
Pin 39
Pin 40
The pinout information for each connector appears below. The tables include the
connections between the FPGA and the expansion connectors plus the signal names used
in the detailed schematic in
48
SRAM
Address
OE#, WE#
Data[7:0] to IC10 only
Figure 13-2: 40-pin Expansion Connector
Figure
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Chapter 13: Expansion Connectors and Boards
JTAG Serial Configuration
√
√
√
Figure 13-2, uses 0.1-inch (100 mil) DIP spacing.
Pin 3: +3.3V Pin 1: GND
Pin 4
A-1.
Spartan-3 Starter Kit Board User Guide
Parallel Configuration
√
Pin 39
Pin 40
Pin 2: VU
+5V
UG130_c12_02_042504
UG130 (v1.1) May 13, 2005