Flash Read" Option - Xilinx Spartan-3 User Manual

"Flash Read" Option

"Flash Read" Option
The Spartan-3 Starter Kit Board includes a 2Mbit Platform Flash configuration PROM. The
XC3S200 FPGA on the board only requires slightly less than 1Mbit for configuration data.
The remainder of the Platform Flash is available to store other non-volatile data, such as
revision codes, serial numbers, coefficients, an Ethernet MAC ID, or code for an embedded
processor, such as MicroBlaze, within the FPGA.
To allow the FPGA to read from Platform Flash after configuration, the JP1 jumper must be
properly positioned, as shown in
Platform Flash is always enabled. After FPGA configuration completes, the FPGA
application drives the INIT_B pin High, FPGA pin N9. Consequently, the Platform Flash
data pointer is not reset and points to the additional data following the FPGA
configuration data. To read any subsequent data, the FPGA application generates
additional clock pulses on the RCLK signal from FPGA pin A14. After configuration, the
FPGA's CCLK output is three-stated with a pull-up resistor to V
Platform Flash presents serial data on the FPGA's DIN pin, pin M11.
The resistor between the CCLK output and FPGA pin A14 prevents any accidental
conflicts between the two signals.
Spartan-3 Starter Kit Board User Guide
UG130 (v1.1) May 13, 2005
Spartan-3 FPGA
M0
M1
M2
J8
Figure 10-1: Default Platform Flash Option
Spartan-3 FPGA
M0
M1
M2
J8
Figure 10-2: Read Additional Data from Platform Flash by Setting the JP1 Jumper
DIN/D0
INIT_B
DONE
CCLK
USER I/O
RCLK
Figure 10-2. When the jumper is in this position, the
(M11)
DIN/D0
(N9)
INIT_B
DONE
CCLK
(A14)
USER I/O
RCLK
(xx) = FPGA pin number
www.xilinx.com
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Platform Flash
D0
Default
OE/RESET
CE
CLK
UG130_c10_01_060704
(2.5V). The
CCAUX
Platform Flash
D0
Flash Read
OE/RESET
CE
CLK
UG130_c10_02_060404
R
JP1
JP1
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