A1 Connector Pinout - Xilinx Spartan-3 User Manual

Expansion Connectors

A1 Connector Pinout

The A1 expansion connector is located along the top edge of the board, on the left, as
indicated by
FPGA connections are specified in parentheses.
Table 13-2: Pinout for A1 Expansion Connector
Schematic Name
GND
V (+3.3V)
CCO
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
LSBCLK
MA1-DB1
MA1-DB3
MA1-DB5
MA1-DB7
MA1-DSTB
MA1-WAIT
MA1-INT
TMS
TDO-ROM
Spartan-3 Starter Kit Board User Guide
UG130 (v1.1) May 13, 2005
in Figure 1-2.
21
FPGA Pin Connector
V (all banks)
CCO
(N7)
SRAM IC10 IO0
(T8)
SRAM IC10 IO1
(R6)
SRAM IC10 IO2
(T5)
SRAM IC10 IO3
(R5)
SRAM IC10 IO4
(C2)
SRAM IC10 IO5
(C1)
SRAM IC10 IO6
(B1)
SRAM IC10 IO7
(M7)
(F3)
SRAM A6
(E3)
SRAM A8
(G5)
SRAM A10
(H4)
SRAM A12
(J3)
SRAM A14
(K5)
SRAM A16
(L3)
SRAM A17
(C13)
FPGA JTAG TMS
Platform Flash
JTAG TDO
www.xilinx.com
1-800-255-7778
Table 13-2 provides the pinout for the A1 connector. The
FPGA Pin
1 2
3 4 (N8)
(L5)
5 6
SRAM A0
(N3)
7 8
SRAM A1
(M4)
9 10
SRAM A2
(M3)
11 12
SRAM A3
(L4)
13 14
SRAM A4
(G3)
15 16
SRAM WE#
(K4)
17 18
SRAM OE#
(P9)
19 20
FPGA DOUT/BUSY
21 22 (M10)
(G4)
23 24
SRAM A5
(F4)
25 26
SRAM A7
(E4)
27 28
SRAM A9
(H3)
29 30
SRAM A11
(J4)
31 32
SRAM A13
(K3)
33 34
SRAM A15
JTAG Isolation
35 36
(C14)
37 38
FPGA JTAG TCK
Header J7, pin 3
39 40
R
Schematic Name
VU (+5V)
ADR0
ADR1
ADR2
ADR3
ADR4
ADR5
WE
OE
CSA
MA1-DB0
MA1-DB2
MA1-DB4
MA1-DB6
MA1-ASTB
MA1-WRITE
MA1-RESET
JTAG Isolation
TCK
TDO-A
49