Timer 0 Control Register - Samsung S3C80A5B User Manual

S3C80A5B
T0CON

— Timer 0 Control Register

Bit Identifier
RESET Value
Read/Write
Addressing Mode
.7–.6
.5–.4
.3
.2
.1
.0
NOTE: A timer 0 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 0
match/ capture interrupt, IRQ0, vector FCH, must be cleared by the interrupt service routine.
.7 .6
0 0
R/W R/W
Register addressing mode only
Timer 0 Input Clock Selection Bits
0 0
f /4096
OSC
0 1
f /256
OSC
1 0
f /8
OSC
1 1
External clock input (at the T0CK pin, P2.1)
Timer 0 Operating Mode Selection Bits
0 0
Interval timer mode (counter cleared by match signal)
0 1
Overflow mode(OVF interrupt can occur)
1 0
Overflow mode( OVF interrupt can occur)
1 1
PWM mode (OVF interrupt can occur)
Timer 0 Counter Clear Bit
0 No effect (when write)
1 Clear T0 counter, T0CNT (when write)
Timer 0 Overflow Interrupt Enable Bit
0 Disable T0 overflow interrupt
1 Enable T0 overflow interrupt
Timer 0 Match Interrupt Enable Bit
0 Disable T0 match interrupt
1 Enable T0 match interrupt
Timer 0 Match Interrupt Pending Flag
0 No T0 match interrupt pending (when read)
0 Clear T0 match interrupt pending condition (when write)
1 T0 match interrupt is pending (when read)
1 No effect (when write)
.5 .4
0 0
R/W R/W R/W
(note)
CONTROL REGISTERS
D2H
.3 .2 .1
0 0 0
R/W R/W
Set 1
.0
0
R/W
4-27