And Logical And - Samsung S3C80A5B User Manual

INSTRUCTION SET
AND
— Logical AND
AND dst,src
dst ← dst AND src
Operation:
The source operand is logically ANDed with the destination operand. The result is stored in the
destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in
the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source
are unaffected.
Flags: C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.
Format:
opc
opc
opc
Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
AND
AND
AND
AND
AND
In the first example, destination working register R1 contains the value 12H and the source working
register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with
the destination operand value 12H, leaving the value 02H in register R1.
6-16
dst | src
src dst
dst src
→ R1 = 02H, R2 = 03H
R1,R2
→ R1 = 02H, R2 = 03H
R1,@R2
→ Register 01H = 01H, register 02H = 03H
01H,02H
01H,@02H → Register 01H = 00H, register 02H = 03H
→ Register 01H = 21H
01H,#25H
Bytes Cycles Opcode
2 4
6
3 6
6
3 6
S3C80A5B
Addr Mode
(Hex) dst src
52 r r
53 r lr
54 R R
55 R IR
56 R IM