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S3C80A5B
INDEXED ADDRESSING MODE (X)
Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate
the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the
internal register file or in external memory (if implemented). You cannot, however, access locations C0H–FFH in
set 1 using Indexed addressing.
In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range –128 to
+127. This applies to external memory accesses only (see Figure 3-8).
For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in
a working register. For external memory accesses, the base address is stored in the working register pair
designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address (see
Figure 3-9).
The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction (LD).
The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data
memory (if implemented).
Two-Operand
Instruction
Example
Sample Instruction:
LD
Program Memory
Base Address
dst/src
x
Point to One of the
OPCODE
Working Register
R0, #BASE[R1]
Figure 3-7. Indexed Addressing to Register File
Register File
MSB Points to
RP0 or RP1
RP0 or RP1
~
Value used in
Instruction
OPERAND
+
~
3 LSBs
(1 of 8)
; Where BASE is an 8-bit immediate value
ADDRESSING MODES
~
Selected RP
Points to
Start of
Working
Register
Block
~
INDEX
3-7
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