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RESET
and POWER-DOWN
POWER-DOWN MODES
STOP MODE
Stop mode is invoked by stop control register (STOPCON) setting and the instruction STOP. In Stop mode, the
operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply current is
reduced to less than 3 uA at 5.5 V. All system functions stop when the clock "freezes,"
Stop mode can be released of two ways : by an INTR (Interrupt with Reset) or by a POR (Power On Reset).
USING POR TO RELEASE STOP MODE
Stop mode is released when the reset signal goes active by power on reset (POR): all system and peripheral control
registers are reset to their default hardware values and the contents of all data registers are unknown states. When
the oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching the
program instruction stored in ROM location 0100H.
USING AN INTR TO RELEASE STOP MODE
Stop mode is released when INTR (Interrupt with Reset) occurs. INTR occurs when falling/rising edge is detected at
P0 during stop mode and it make system reset.
1. Do not use stop mode if you are using an external clock source because X
internally to V
SS
2. STOP mode always be released by the system reset (INTR or POR) so the system register value and
control register value are initialized as reset value. And when the reset occurs from INTR, the prime
register value will be retained but it will be unknown states if it occurs from POR. So an application
which is using stop mode should be added specific S/W which divide the system reset into STOP
mode releasing or power on reset. Following Programming Tip can be useful for more
understanding.
8-6
to reduce current leakage.
NOTES
input must be cleared
IN
S3C80A5B
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