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RESET
S3C80A5B
and POWER-DOWN
8
RESET and POWER-DOWN
SYSTEM RESET
S3C80A5B has four different system reset sources as followings:
— Low Voltage Detect (LVD)
— Internal POR circuit
— INTR (Interrupt with RESET)
— Basic Timer (Watchdog timer)
Enable/Disable
Noise
LVD
Filter
Stop
STOPCON
INTR
POR
BT(WDT)
Figure 8-1. Rese t Block Diagram
LVD RESET
The Low Voltage detect circuit is built on the S3C80A5B product for system reset not in stop mode. When the
operating status is not stop mode it detects a slope of V
by comparing the voltage at V
with V
(Low level
DD
DD
LVD
Detect Voltage). The reset pulse is generated by the rising slope of V
. While the voltage at V
is rising up and
DD
DD
>= V
passing V
, the reset pulse is occurred at the moment "V
". This function is disabled when the
LVD
DD
LVD
operating state is "stop mode" to reduce the current consumption under 1 uA instead of 6 uA.
8-1
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