Interrupt Priority Register (Ipr) - Samsung S3C80A5B User Manual

8-bit cmos
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S3C80A5B
Group priority:
D7 D4 D1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
NOTE: In this device interrupt structure, only levels IRQ0, IRQ1, IRQ4, IRQ6-IRQ7

Interrupt Priority Register (IPR)

FFH, Set 1, Bank 0, R/W
MSB
.7
.6
.5
=
Undefined
= B > C > A
= A > B > C
= B > A > C
= C > A > B
= C > B > A
= A > C > B
=
Undefined
0 = IRQ6 > IRQ7
1 = IRQ7 > IRQ6
are used. Settings for group/subgroup B, which control relative priorities for
levels IRQ2, IRQ3 and IRQ5, are therefore not evaluated.
Figure 5-8. Interrupt Priority Register (IPR)
.4
.3
.2
Subgroup B
0 = IRQ4
1 = IRQ4
(note)
Group C
0 = IRQ6, IRQ7
1 = IRQ6, IRQ7
Subgroup C
INTERRUPT STRUCTURE
.1
.0
LSB
Group A
0 = IRQ0 > IRQ1
1 = IRQ1 > IRQ0
(note)
Group B
0 = IRQ4
1 = IRQ4
(note)
5-13

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