Counter A Block Diagram - Samsung S3C80A5B User Manual

COUNTER A
DIV 1
DIV 2
DIV 4
DIV 8
f
OSC
CACON.2
NOTE: The value of the CADATAL register is loaded into the 8-bit counter when the operaion of the counter A
Starts. If a borrow occurs in the counter, the value of the CADATAH register is loaded into the 8-bit
counter. However, if the next borrow ovvurs, the value of the CADATAL register is loaded into the 8-bit
counter.
12-2
CACON.6-.7
CLK
MUX
Repeat
Control
Interrupt
Control
Counter A Data
Low Byte Register
CACON.4-.5
Counter A Data
High Byte Register
Figure 12-1. Counter A Block Diagram
8-Bit
Down Counter
MUX
INT.GEN.
Data Bus
CACON.0
To Other Block
(CAOF)
(P3.1/REM)
CACON.3
IRQ4
(CAINT)
S3C80A5B