Timer 1 Control Register (T1Con) - Samsung S3C80A5B User Manual

TIMER 1

TIMER 1 CONTROL REGISTER (T1CON)

The timer 1 control register, T1CON, is located in set 1, FAH, and is read/write addressable. T1CON contains
control settings for the following T1 functions:
— Timer 1 input clock selection
— Timer 1 operating mode selection
— Timer 1 16-bit down counter clear
— Timer 1 overflow interrupt enable/disable
— Timer 1 match interrupt enable/disable
— Timer 1 interrupt pending control (read for status, write to clear)
A reset operation clears T1CON to '00H', selecting f
normal interval timer, and disabling the timer 1 interrupts.
MSB
Timer 1 input clock selection bits:
00 = f /4
OSC
01 = f /8
OSC
10 = f /16
OSC
11 = Internal clock (T-F/F)
Timer 1 operating mode selection bits:
00 = Interval mode
01 = Overflow mode (OVF interrupt can occur)
01 = Overflow mode (OVF interrupt can occur)
01 = Overflow mode (OVF interrupt can occur)
11-4
OSC
Timer 1 Control Register (T1CON)
FAH, R/W
.7 .6 .5 .4
Timer 1 counter clear bit:
0 = No effect
1 = Clear the timer 1 counter (when write)
Figure 11-3. Timer 1 Control Register (T1CON)
divided by 4 as the T1 clock, configuring timer 1 as a
.3 .2 .1 .0
Timer 1 match interrupt pending bit:
0 = No interrupt pending
0 = Clear pending bit (write)
1 = Interrupt is pending
Timer 1 match interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
Timer 1 overflow interrupt enable bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
LSB
S3C80A5B