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TIMER 1
TIMER 1 OVERFLOW INTERRUPT
Timer 1 can be programmed to generate an overflow interrupt (IRQ1, F4H) whenever an overflow occurs in the 16-bit
up counter. When you set the timer 1 overflow interrupt enable bit, T1CON.2, to "1", the overflow interrupt is
generated each time the 16-bit up counter reaches 'FFFFH'. After the interrupt request is generated, the counter
value is automatically cleared to '00H' and up counting resumes. By writing a "1" to T1CON.3, you can clear/reset
the 16-bit counter value at any time during program operation.
TIMER 1 MATCH INTERRUPT
Timer 1 can also be used to generate a match interrupt (IRQ1, vector F6H) whenever the 16-bit counter value
matches the value that is written to the timer 1 reference data registers, T1DATAH and T1DATAL. When a match
condition is detected by the 16-bit comparator, the match interrupt is generated, the counter value is cleared, and up
counting resumes from '00H'.
In match mode, program software can poll the timer 1 match interrupt pending bit, T1CON.0, to detect when a timer
1 match interrupt pending condition exists (T1CON.0 = "1"). When the interrupt request is acknowledged by the
CPU and the service routine starts, the interrupt service routine for vector F6H must clear the interrupt pending
condition by writing a "0" to T1CON.0.
CLK
Figure 11-1. Simplified Timer 1 Function Diagram: Interval Timer Mode
11-2
Interrupt
Enable/Disable
(T1CON.2)
16-Bit UP Counter
(Read-Only)
16-Bit Comparator
Timer 1 High/Low
Buffer Register
Timer 1 Data High/Low
Buffer Register
IRQ1(T1INT)
Pending
(T1CON.0)
R (Clear)
Match
Match Signal
T1CON.3
S3C80A5B
CTL
T1CON.5
T1CON.4
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