S3C80A5B Interrupt Structure - Samsung S3C80A5B User Manual

INTERRUPT STRUCTURE
Levels
RESET
IRQ0
IRQ1
IRQ4
IRQ6
IRQ7
NOTE: For interrupt levels with two or more vectors, the lowest vector address
5-4
Vectors
100H
1
FCH
0
FAH
1
F6H
0
F4H
ECH
3
E6H
2
E4H
1
E2H
0
E0H
E8H
usually the highest priority. For example, FAH has the higher priority (0)
than FCH (1) within level IRQ0. These priorities are fixed in hardware.
Figure 5-2. S3C80A5B Interrupt Structure
Sources
Basic timer overflow/INTR/POR
Timer 0 match
Timer 0 overflow
Timer 1 match
Timer 1 overflow
Counter A
P0.3 external interrupt
P0.2 external interrupt
P0.1 external interrupt
P0.0 external interrupt
P0.7 external interrupt
P0.6 external interrupt
P0.5 external interrupt
P0.4 external interrupt
S3C80A5B
Reset/Clear
H/W
S/W
H/W
S/W
H/W
H/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W