Counter A Control Register (Cacon) - Samsung S3C80A5B User Manual

S3C80A5B

COUNTER A CONTROL REGISTER (CACON)

The counter A control register, CACON, is located in set 1, bank 0, F3H, and is read/write addressable. CACON
contains control settings for the following functions (see Figure 12-2):
— Counter A clock source selection
— Counter A interrupt enable/disable
— Counter A interrupt pending control (read for status, write to clear)
— Counter A interrupt time selection
MSB
Counter A input clock
selection bits:
00 = f
01 = f
10 = f
11 = f
Counter A interrupt selection bits:
00 = Elapsed time for Low data value
01 = Elapsed time for High data value
10 = Elapsed time for Low and High
11 = Invalid setting
Counter A Control Register (CACON)
F3H, Set 1, R/W
.7 .6 .5
OSC
/2
OSC
/4
OSC
/8
OSC
data values
Figure 12-2. Counter A Control Register (CACON)
.4 .3 .2 .1
Counter A output flip-flop
control bit:
0 = T-FF is Low
1 = T-FF is High
Counter A mode selection bit:
0 = One-shot mode
1 = Repeating mode
Counter A start/stop bit:
0 = Stop counter A
1 = Start counter A
Counter A interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
.0
LSB
COUNTER A
12-3