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S3C80A5B
PORT 0
Port 0 is a general-purpose, 8-bit I/O port. It is bit-programmable. Port 0 pins are accessed directly by read/write
operations to the port 0 data register, P0 (set 1, E0H). The P0 pin circuits support pull-up resistor assignment using
P0PUR register settings and all pins have noise filters for external interrupt inputs.
Two 8-bit control registers are used to configure port 0 pins: P0CONH (set 1, E8H) for the upper nibble pins, P0.7–
P0.4, and P0CONL (set 1, E9H) for lower nibble pins, P0.3–P0.0. Each control register byte contains four bit-pairs
and each bit-pair configures one pin (see Figures 9-2 and 9-3). A hardware reset clears all P0 control and data
registers to '00H'.
A separate register, the port 0 interrupt control register, P0INT (set 1, F1H), is used to enable and disable external
interrupt input. You can poll the port 0 interrupt pending register, P0PND to detect and clear pending conditions for
these interrupts.
The lower-nibble pins, P0.3–P0.0, are used for INT3–INT0 input (IRQ6), respectively. The upper nibble pins, P0.7–
P0.4, are all used for INT4 input (IRQ7). Interrupts that are detected at any of these four pins are processed using the
same vector address (E8H).
Port 0 , P0.0–P0.7, is assigned interrupt with reset(INTR) to release stop mode with system reset.
Port 0 Control Register, High Byte (P0CONH)
MSB
.7
.6
.5
P0.6/INT4
P0.7/INT4
P0CONH Pin Configureation Settings:
00
Input mode; interrupt on falling edges
01
Input mode; interrupt on rising and falling edges
10
Push-pull output mode
11
Input mode; interrupt on rising edges
Figure 9-2. Port 0 High-Byte Control Register (P0CONH)
E8H, Set 1, R/W
.4
.3
.2
P0.4/INT4
P0.5/INT4
.1
.0
LSB
I/O PORTS
9-3
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