Irq Interrupt Request Register - Samsung S3C80A5B User Manual

S3C80A5B
IRQ
— Interrupt Request Register
Bit Identifier
RESET Value
Read/Write
Addressing Mode
.7
.6
.5
.4
.3–.2
.1
.0
NOTE: Interrupt level IRQ2, IRQ3 and IRQ5 is not used in the S3C80A5B interrupt structure.
.7 .6
0 0
R R
Register addressing mode only
Level 7 (IRQ7) Request Pending Bit; External Interrupts P0.7–P0.4
0 Not pending
1 Pending
Level 6 (IRQ6) Request Pending Bit; External Interrupts P0.3–P0.0
0 Not pending
1 Pending
Not used for S3C80A5B.
Level 4 (IRQ4) Request Pending Bit; Counter A Interrupt
0 Not pending
1 Pending
Not used for S3C80A5B.
Level 1 (IRQ1) Request Pending Bit; Timer 1 Match or Overflow
0 Not pending
1 Pending
Level 0 (IRQ0) Request Pending Bit; Timer 0 Match or Overflow
0 Not pending
1 Pending
.5 .4 .3
0 0 0
R R R
CONTROL REGISTERS
DCH
.2 .1
0 0
R R
Set 1
.0
0
R
4-13