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S3C80A5B
DA
— Decimal Adjust
DA
dst
dst ← DA dst
Operation:
The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction
operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the
operation performed. (The operation is undefined if the destination operand was not the result of a
valid addition or subtraction of BCD digits):
Instruction
Carry
Before DA
ADD
ADC
SUB
SBC
Flags:
C: Set if there was a carry from the most significant bit; cleared otherwise (see table).
Z: Set if result is "0"; cleared otherwise.
S: Set if result bit 7 is set; cleared otherwise.
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
opc
Bits 4–7
Value (Hex)
0
0–9
0
0–8
0
0–9
0
A–F
0
9–F
0
A–F
1
0–2
1
0–2
1
0–3
0
0–9
0
0–8
1
7–F
1
6–F
dst
H Flag
Bits 0–3
Before DA
Value (Hex)
0
0–9
0
A–F
1
0–3
0
0–9
0
A–F
1
0–3
0
0–9
0
A–F
1
0–3
0
0–9
1
6–F
0
0–9
1
6–F
Bytes
2
INSTRUCTION SET
Number Added
to Byte
00
06
06
60
66
66
60
66
66
00 = – 00
FA = – 06
A0 = – 60
9A = – 66
Cycles
Opcode
(Hex)
4
40
4
41
Carry
After DA
0
0
0
1
1
1
1
1
1
0
0
1
1
Addr Mode
dst
R
IR
6-33
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