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ADDRESS SPACES
S3C80A5B
REGISTER SET 1
The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH.
In some S3C8-series microcontrollers, the upper 32-byte area of this 64-byte space (E0H–FFH) is divided into two
32-byte register banks, bank 0 and bank 1. The set register bank instructions SB0 or SB1 are used to address one
bank or the other. In the S3C80A5B microcontroller, bank 1 is not implemented. A hardware reset operation
therefore always selects bank 0 addressing, and the SB0 and SB1 instructions are not necessary.
The upper 32-byte area of set 1 (FFH–E0H) contains 26 mapped system and peripheral control registers. The lower
32-byte area contains 16 system registers (DFH–D0H) and a 16-byte common working register area (CFH–C0H).
You can use the common working register area as a "scratch" area for data operations being performed in other
areas of the register file.
Registers in set 1 locations are directly accessible at all times using the Register addressing mode. The 16-byte
working register area can only be accessed using working register addressing. (For more information about working
register addressing, please refer to Section 3, "Addressing Modes," .)
REGISTER SET 2
The same 64-byte physical space that is used for set 1 locations C0H–FFH is logically duplicated to add another 64
bytes of register space. This expanded area of the register file is called set 2. All set 2 locations (C0H–FFH) are
addressed as part of page 0 in the S3C80A5B register space.
The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions: You can use only
Register addressing mode to access set 1 locations; to access registers in set 2, you must use Register Indirect
addressing mode or Indexed addressing mode.
The set 2 register area is commonly used for stack operations.
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