Port 0 Control Register (Low Byte) - Samsung S3C80A5B User Manual

8-bit cmos
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S3C80A5B
P0CONL

— Port 0 Control Register (Low Byte)

Bit Identifier
RESET Value
Read/Write
Addressing Mode
.7–.6
.5–.4
.3–.2
.1–.0
NOTES:
1.
The INT3–INT0 external interrupts at P0.3–P0.0 are interrupt level IRQ6. Each interrupt has a separate vector
address.
2.
You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR register.
.7
.6
0
0
R/W
R/W
Register addressing mode only
P0.3/INT3 Mode Selection Bits
0
0
C-MOS input mode; interrupt on falling edges
0
1
C-MOS input mode; interrupt on rising and falling edges
1
0
Push-pull output mode
1
1
C-MOS input mode; interrupt on rising edges
P0.2/INT2 Mode Selection Bits
0
0
C-MOS input mode; interrupt on falling edges
0
1
C-MOS input mode; interrupt on rising and falling edges
1
0
Push-pull output mode
1
1
C-MOS input mode; interrupt on rising edges
P0.1/INT1 Mode Selection Bits
0
0
C-MOS input mode; interrupt on falling edges
0
1
C-MOS input mode; interrupt on rising and falling edges
1
0
Push-pull output mode
1
1
C-MOS input mode; interrupt on rising edges
P0.0/INT0 Mode Selection Bits
0
0
C-MOS input mode; interrupt on falling edges
0
1
C-MOS input mode; interrupt on rising and falling edges
1
0
Push-pull output mode
1
1
C-MOS input mode; interrupt on rising edges
.5
.4
0
0
R/W
R/W
R/W
CONTROL REGISTERS
E9H
.3
.2
.1
0
0
0
R/W
R/W
Set 1
.0
0
R/W
4-15

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