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INTERRUPT STRUCTURE
INTERRUPT PRIORITY REGISTER (IPR)
The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels
used in the microcontroller's interrupt structure. After a reset, all IPR bit values are undetermined and must
therefore be written to their required settings by the initialization routine.
When more than one interrupt source is active, the source with the highest priority level is serviced first. If both
sources belong to the same interrupt level, the source with the lowest vector address usually has priority (This
priority is fixed in hardware).
To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by
the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register
priority definitions (see Figure 5-7):
Group A
Group B
Group C
As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C.
For example, the setting '001B' for these bits would select the group relationship B > C > A; the setting '101B'
would select the relationship C > B > A.
The functions of the other IPR bit settings are as follows:
— IPR.5 controls the relative priorities of group C interrupts.
— Interrupt group B has a subgroup to provide an additional priority relationship between for interrupt levels 2, 3,
and 4. IPR.3 defines the possible subgroup B relationships. IPR.2 controls interrupt group B. In the
S3C80A5B implementation, interrupt levels 2 and 3 are not used. Therefore, IPR.2 and IPR.3 settings are not
evaluated, as IRQ4 is the only remaining level in the group.
— IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.
5-12
IRQ0, IRQ1
IRQ4
IRQ6, IRQ7
IPR
Group A
A1
A2
IRQ0
IRQ1
Figure 5-7. Interrupt Request Priority Groups
IPR
Group B
C1
IRQ4
IRQ6
IPR
Group C
C2
IRQ7
S3C80A5B
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