Band Bit And - Samsung S3C80A5B User Manual

S3C80A5B
BAND
— Bit AND
BAND dst,src.b
BAND dst.b,src
dst(0) ← dst(0) AND src(b)
Operation:
or
dst(b) ← dst(b) AND src(0)
The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the
destination (or source). The resultant bit is stored in the specified bit of the destination. No other
bits of the destination are affected. The source is unaffected.
Flags: C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
opc
opc
NOTE:
Examples: Given: R1 = 07H and register 01H = 05H:
BAND R1,01H.1
BAND 01H.1,R1
In the first example, source register 01H contains the value 05H (00000101B) and destination
working register R1 contains 07H (00000111B). The statement "BAND R1,01H.1" ANDs the bit 1
value of the source register ("0") with the bit 0 value of register R1 (destination), leaving the value
06H (00000110B) in register R1.
src
dst | b | 0
dst
src | b | 1
In the second byte of the 3-byte instruction formats, the destination (or source) address is four
bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.
→ R1 = 06H, register 01H = 05H
→ Register 01H = 05H, R1 = 07H
Bytes Cycles Opcode
3 6
3 6
INSTRUCTION SET
Addr Mode
(Hex) dst src
67 r0 Rb
67 Rb r0
6-17