Power - Samsung S5PV210 Hardware Design Manual

S5PV210_HARDWARE DESING GUIDE REV 1.0

3. Power

3.1. Pin Power Domain
Power Ball
Group
Name
DIGITAL
IO
VDD_M2
POWER
VDD_M1
VDD_M0
VDD_LCD
VDD_CAM
VDD_AUD
VDD_MODEM
VDD_KEY
VDD_SYS0
VDD_SYS1
VDD_EXT0
VDD_EXT1
Signal Ball Name
XM2ADDR[13:0],XM2BA[1:0],XM2CASN,XM2RASN,
XM2WEN,XM2CKE0,XM2CKE1/ADDR14,XM2CSN[1:0],
XM2DQS[3:0],XM2DQSN[3:0],XM2DM[3:0],XM2SCLK,
XM2SCLKN,XM2DATA[31:0]
XM1ADDR[13:0],XM1BA[1:0],XM1CASN,XM1RASN,
XM1WEN,XM1CKE0,XM1CKE1/ADDR14,XM1CSN[1:0],
XM1DQS[3:0],XM1DQSN[3:0],XM1DM[3:0],XM1SCLK,
XM1SCLKN,XM1DATA[31:0]
XM0ADDR_[15:0],XM0BEN_[1:0],XM0CSN_[5:0],
XM0DATA_[15:0],XM0DATA_RDN,XM0FALE,XM0FCLE,
XM0FREN,XM0FRNB_[3:0],XM0FWEN,XM0OEN,XM0WAITN,
XM0WEN, XEFFSOURCE_0
XVHSYNC,XVSYS_OE,XVVCLK,XVVD_[23:0],XVVDEN,
XVVSYNC,XVVSYNC_LDI
XCICLKENB,XCIDATA_[7:0],XCIFIELD,XCIHREF,XCIPCLK,
XCIVSYNC
XI2S0CDCLK,XI2S0LRCK,XI2S0SCLK,XI2S0SDI,
XI2S0SDO_[2:0],XI2S1CDCLK,XI2S1LRCK,XI2S1SCLK,
XI2S1SDI,XI2S1SDO,XPCM2EXTCLK,XPCM2FSYNC,
XPCM2SCLK,XPCM2SIN,XPCM2SOUT,XCLKOUT
XMSMADDR_[13:0],XMSMADVN,XMSMCSN,
XMSMDATA_[15:0],XMSMIRQN,XMSMRN,XMSMWEN
XEINT_[31:16]
XXTI,XXTO,XOM_[5:0],XPWRRGTON,XNRESET,XNRSTOUT,XN
WRESET,XEINT_[7:0],XUOTGDRVVBUS,XUHOSTPWREN,XUH
OSTOVERCUR,XDDR2SEL,XUSBXTI,XUSBXTO,XJTRSTN,XJTM
S,XJTCK,XJTDI,XJTDO,XJDBGSEL
XEINT_[15:8]
XMMC0CDN,XMMC0CLK,XMMC0CMD,XMMC0DATA_[3:0],
XMMC1CDN,XMMC1CLK,XMMC1CMD,XMMC1DATA_[3:0],
XSPICLK_0,XSPICSN_0,XSPIMISO_0,XSPIMOSI_0,XURXD_0,
XUTXD_0,XUCTSN_0,XURTSN_0,XURXD_1,XUTXD_1,
XUCTSN_1,XURTSN_1,XI2C0SDA,XI2C0SCL,
XPWMTOUT_[3:0]
XMMC2CDN,XMMC2CLK,XMMC2CMD,XMMC2DATA_[3:0],
XI2C1SCL,XI2C1SDA,XI2C2SCL,XI2C2SDA,XURXD_2,
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