Status Byte Register - Anritsu MT9083 Series Operation Manual

Chapter 2 Before use

2.6.2 Status Byte Register

2-12
The meaning of each bit of the status byte register is shown in the
following table.
Table 2.6.2-1 Meaning of Status Byte Register
Bit
7 OSR (Operation Status Register)
Displays the equipment's operation status. Currently
only 1 can be set during OTDR measurement. This is
the logical sum of each bit of the logical product of the
operation event register and status operation enable
register.
6 MSS (Master Summary Register)
This indicates whether the value read from the status
byte register is 0 or not.
It is the logical sum of the logical product of the status
byte register and the service request enable register.
5 ESB (Event Status Bit)
This is the logical sum of each bit of the logical product
of the standard event status register and standard
event enable register.
4 MAV (Message AVailable summary)
This is always 0 in this instrument, because messages
are not spooled and are sent immediately.
3 Questionable Status Register
Not used; always 0
2 Error / Event Queue
This is 1 when there is an error message in the Error
queue.
1 Not used; always 0
0 Not used; always 0
Bit 7 to bit 0 of the status byte register can be read with *STB . The *SRE
and *SRE? common commands can be used for setting and reading the
service request enable register for setting reading of the status byte
register. To output the status byte register data, set the bit corresponding
to the service request enable register to 1.
Bits 5, 3, and 2 of the status byte register can be set to 0 using the *CLS
common command.
When *CLS is sent after a command or when a query is sent after *CLS ,
the send queue is cleared and bit 4 is set to 0.
The service request enable register cannot be set to 0 using *CLS , so use
*SRE .
Explanation