Mitsubishi Electric FX3G SERIES Programming Manual page 406

Programmable controllers
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FX
/FX
/FX
Series Programmable Controllers
3G
3U
3UC
Programming Manual - Basic & Applied Instruction Edition
1)
Write the following data to [
S
[
+ 1,
1
[
S
+ 5,
1
S
[
+ 9,
1
S
[
+ 13,
1
S
[
+ 4n - 3,
1
For example, store the 32-bit rising point data to devices having an even device number, and store the 32-bit
falling data to devices having an odd device number.
When the command input is set to ON, "n" points starting from
Each rising point/falling point can be changed respectively by overwriting the data in [
D
S
[
+4n-1,
1
1
D
D
+1
D
+2
D
+3
0
Cautions
1. Specifying a high-speed counter (C235 to C255)
In DABSD instruction, a high seed counter can be specified as
In this case, however, the output pattern contains response delay caused by the scan cycle with regard to the current
value of a counter.
When high responsitivity is required in FX
the HSZ instruction, or use the HSCT instruction.
2. When specifying digits of a bit device as
1)
Device number
Specify a multiple of 16 (0, 16, 32, 64 ...).
2)
Number of digits
- In ABSD instruction (16-bit operation): Only K4 is available.
- In DABSD instruction (32-bit operation): Only K8 is available.
3. Other cautions
• The value "n" determines the number of target outputs (1 ≤ n ≤ 64).
• Even if the command input is set to OFF, the ON/OFF status of outputs does not change.
404
D
S
D
S
,
1
1
1
1
Rising point
Data value
(example)
S
]
1
100
S
+ 4]
1
160
S
+ 8]
1
240
S
+ 12]
1
S
+ 4n - 4]
1
D
S
+4n-2].
1
1
40
140
100
60
160
180
14.3 FNC 62 – ABSD / Absolute Drum Sequencer
D
S
D
S
+1] to [
+4n-2,
1
1
1
1
40
S
S
[
+ 3,
+ 2]
1
1
[
S
+ 7,
S
+ 6]
1
1
S
S
[
+ 11,
+ 10]
1
1
S
S
[
+ 15,
+ 14]
1
1
S
S
[
+ 4n - 1,
1
1
D
D
200
240
280
360
D
S
.
1
2
/FX
PLCs, use the table high-speed comparison function offered by
3U
3UC
S
D
1
1
14 Handy Instruction – FNC 60 to FNC 69
+4n-1] in advance using a transfer instruction:
Falling point
Data value
(example)
140
200
60
280
+ 4n - 2]
change as shown below.
1
Target output
D
D
+1
D
+2
D
+3
+ n − 1
D
S
D
D
S
+1,
] to
1
1
1
1

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