Orban OPTIMOD-FM 8500S Operating Manual page 88

2-32
INSTALLATION
If you are required to implement the average modulation limits specified
by ITU-R 412-9, you may seldom see peaks hitting ±75 kHz deviation. In
this case, we advise you to set the output level by using the 8500S's ref-
erence 100Hz tone.
In the United States, F.C.C. Rules permit you to add 0.5% modulation for
every 1% increase in subcarrier injection. For example, if your subcarrier
injection totals 20%, you can set the total modulation to 110% (±82.5
kHz deviation). This implies that you must set the 8500S's composite out-
put level for the equivalent of 90% modulation, not counting the subcar-
riers. (90% + 20% = 110%.) The pilot injection will thus be about 8%
modulation instead of the desired 9%. Adjust the
E > Next > P
NCODER
lation (±6.75 kHz deviation). This will ordinarily require you to set the
P L parameter to "10%."
ILOT VL
11. Set digital output and configuration level.
[Skip this step if you will not be using the digital outputs.]
[See the notes in step 10 immediately above.]
A) Navigate to Setup > I/O C
B) Set the DO P -E control to P
RE
C) Set the DO R
ATE
The 8500S's fundamental sample rate is always 32 kHz, ensuring that the
output bandwidth is always strictly limited to 16 kHz and that the proc-
essed signal can be passed through a 32 kHz uncompressed STL without
addition of overshoot. However, the internal sample rate converter sets
the rate at the 8500S's digital output. This adjustment allows you to set
the output sample rate to ensure compatibility with equipment requiring
a fixed sample rate.
D) Set the P S
ILOT YNC
The P
S
ILOT YNC
which the 19 kHz pilot tone frequency is locked. (To do this, the DSP clock
is locked to this frequency.) The choices are D
nal appearing at the 8500S's digital input), R
wordclock applied to the 8500S's R
or I (the internal crystal-controlled DSP clock oscillator).
NTERNAL
•
If D I is chosen and no valid signal is available at the unit's digital input, the
IG N
8500S automatically switches the sync source to the R
there is no valid digital input signal at the reference input, the sync source de-
faults to the 8500S's internal clock.
•
If R I is chosen and there is no valid input signal at the R
EF N
tor, the sync source defaults to the 8500S's internal clock.
E) Press Next. Then set the DO S
You can choose P
mined by the P
chronized to the sample rate appearing at the 8500S's XLR AES3 input, or
L
control as necessary to produce 9% modu-
ILOT VL
> D O
ALIB IG UT
-E (for pre-emphasis), P
RE
to 32, 44.1, 48, 88.2, or 96 kHz.
.
control determines the reference frequency source to
I
EF
.
YNC
S (the DSP clock frequency reference as deter-
ILOT YNC
S control), D
ILOT YNC
Setup > S
1 C .
ALIB
+J17, J.17 or F
RE
(the AES3 or AES11 sig-
I
IG N
I (the 10 MHz or 1x
EF N
BNC connector), D
N IG
BNC connector. If
I
EF N
I
EF N
1 I (the output sample rate is syn-
IG N
ORBAN MODEL
TEREO
.
LAT
1 I , D 2 I ,
N IG N
BNC connec-