Orban OPTIMOD-FM 8500S Operating Manual page 292

6-10
TECHNICAL DATA
and scales the signal to the proper level for the analog-to-digital (A/D) con-
verter IC208. IC207A and associated components comprise a servo amp to cor-
rectly DC-bias the signal feeding the A/D converter. R253, R255-R257, C217,
C219 make an attenuator / RC filter necessary to filter high frequency energy
that would otherwise cause aliasing distortion in the A/D converter.
The corresponding right channel circuitry is functionally identical to that just
described.
IC201 and IC202 are through-hole parts, which permits easy field replacement
using simple tools. All other circuitry is surface-mounted. Replacement re-
quires surface-mount rework tools and skills to prevent circuit board damage.
Stereo Analog-to-Digital (A/D) Converter
Located on input/output/DSP board
The A/D converter, IC208, is a stereo 24-bit sigma-delta converter. (This is a sur-
face-mount part and is not field-replaceable.)
The A/D oversamples the audio, applies noise shaping, and emits a bitstream at
64 kHz sample rate.
Digital Input Receiver and Sample Rate Converter (SRC)
Located on input/output/DSP board
The receiver IC501A accepts digital audio signals using the AES3 interface format
(AES3-1992). It applies its output to sample rate converter (SRC) IC503B. This ac-
cepts and sample-rate converts any of the standard 32 kHz, 44.1 kHz, 48 kHz,
88.2 kHz, and 96 kHz rates in addition to any digital audio sample rate within
the range of 32 kHz and 96 kHz. The SRC converts the input sample rate to 64
kHz for processing by the DSP.
Wordclock/10 MHz Sync Reference Input
Located on input/output/DSP board
The 8500S's internal system clock (which drives the DSPs) can be synchronized to
a wordclock or 10 MHz reference applied to J502A. This allows the 19 kHz pilot
tone in the 8500S's composite output to be frequency-synchronized to an accu-
rate frequency standard like GPS or a rubidium-disciplined oscillator.
The input reference waveform is converted to a square wave via IC505 and asso-
ciated circuitry, which implement a comparator with hysteresis. IC1103 is a CPLD
(complex programmable logic device) that accepts the reference square wave.
IC1001 is a PIC microcontroller that measures the frequency of the reference
square wave and (re)configures the CPLD as directed by the main microprocessor.
In turn, the CPLD works with IC1101, IC1102, and IC1104 to implement a phase-
locked loop to generate the system clocks. IC1104 is the phase comparator. The
single-order loop filter consists of R1100, R1106, R1107 and C1100. The 27 MHz
voltage-controlled oscillator IC1101 receives the output of the loop filter. The
output of IC1101 drives IC1102, which is a phase-locked loop frequency genera-
ORBAN MODEL 8500S